A programmable logic array (PLA) is a programmable device used to implement combinational logic circuits. The PLA has a set of programmable AND planes, which link to a set of programmable OR planes, which can then be conditionally complemented to produce an output. This layout allows for a large number of logic functions to be synthesized, including XOR or more complex combinational functions. Many PLAs are mask-programmed during manufacture in the same manner as a ROM. This is particularly true of PLAs that are embedded in more complex and numerous integrated circuits such as microprocessors. PLAs that can be programmed after manufacture are called FPLAs (field-programmable PLAs) or FPGAs (field-programmable gate arrays). FPGA interconnects can be programmed (i.e., “burned in”) only once by the customer or designer, after the FPGA is manufactured, to implement any logical function-hence the name “field-programmable”. FPGAs are usually slower and may draw more power than their application-specific integrated circuit (ASIC) counterparts.
With FPGA, there is a considerable portion of chip space either dedicated to overhead or which is unused. For example, to accommodate a specific application requiring a particular choice or mix of AND and OR gate logic, both must be available in a generic chip, and only those components required for the application are wired, or “burned-in” at programming time.
Magnetoresistance random access memory (MRAM) is a memory element base on the tunneling resistance of an oxide sandwiched between two magnetic layers. When the magnetization in the two layers are parallel, the tunneling resistance is “low,” and this is referred to as a State 0. When the magnetization in the two layers are anti-parallel, the tunneling resistance is “high,” and this is referred to as a State 1. In an MRAM, one layer is fixed for the life of the device, and the other is a “free” layer that can be changed with addressable write lines to generate a magnetic field capable of realligning, or “flipping,” the polarization direction. The State 0 or 1 can be determined by measuring the resistance of the MRAM with a voltage divider circuit relative to a known reference resistance. The State of the MRAM, while being re-writable, is non-volatile, and therefore requires no power to be sustained.
MRAM memory, however, requires switching power levels that are not compatible with battery powered portable devices, and does not scale well as is currently being required in increasingly higher device pitch density.
Presently, logic circuitry does not exist that provides re-programmable logic within a fixed topological configuration of cells relying on non-volatile magnetic memory-type elements. Based on the foregoing, those skilled in the art will appreciate that a need exists for a system providing non-volatile and reconfigurable (i.e., reprogrammable) logic that is scalable to higher device pitch density.